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INTEGRATED CIRCUITS
GTL2006 13-bit GTL-/GTL/GTL+ to LVTTL translator
Product data Supersedes data of 2003 Dec 18 2004 Jun 21
Philips Semiconductors
Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
FEATURES
* Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or * 3.0 V to 3.6 V operation * LVTTL I/O not 5 V tolerant * Series termination on the LVTTL outputs of 30 * ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101 LVTTL to GTL-/GTL/GTL+ driver
PIN CONFIGURATION
VREF 1 1AO 2 2AO 3 5A 4 6A 5 8AI 6 11BI 7 11A 8 9BI 9 3AO 10 4AO 11 10AI1 12 10AI2 13 GND 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC 1BI 2BI 7BO1 7BO2 8BO 11BO 5BI 6BI 3BI 4BI 10BOI 10BO2 9AO
* Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 500 mA
* Package offered: TSSOP28
DESCRIPTION
The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the XeonTM processor GTL-/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications.
SW01091
Figure 1. Pin configuration
PIN DESCRIPTION
PIN NUMBER 1 2-6, 8, 10-13, 15 7, 9, 16, 17-27 14 28 SYMBOL VREF nAn nBn GND VCC NAME AND FUNCTION GTL reference voltage Data inputs/outputs (LVTTL) Data inputs/outputs (GTL-/GTL/GTL+) Ground (0 V) Positive supply voltage
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CI/O PARAMETER Propagation delay An to Bn or Bn to An I/O pin capacitance CONDITIONS Tamb = 25 C CL = 50 pF; VCC = 3.3 V Outputs disabled; VI/O = 0 V or 3.0 V TYPICAL UNIT B to A 5.5 7.8 A to B 5.5 4.5 ns pF
ORDERING INFORMATION
PACKAGES 28-Pin Plastic TSSOP TEMPERATURE RANGE -40 C to +85 C ORDER CODE GTL2006PW TOPSIDE MARK GTL2006 DWG NUMBER SOT361-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
FUNCTION TABLES
INPUT 1BI/2BI/3BI/4BI/9BI L H INPUT 10AI1/10AI2 L L H H OUTPUT 1AO/2AO/3AO/4AO/9AO L H INPUT 9BI L H L H INPUT 8AI L H OUTPUT 10BO1/10BO2 L L L H OUTPUT 8BO L H
INPUT 5BI/6BI L H H
INPUT/OUTPUT 5A/6A (OPEN DRAIN) L L2 H
OUTPUT 7BO1/7BO2 H1 L H
INPUT 11BI L L H
INPUT/OUTPUT 11A (OPEN DRAIN) H L2 L
OUTPUT 11BO L H H
H = HIGH voltage level L = LOW voltage level NOTES: 1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. 2. Open Drain Input/Output terminal is driven to logic LOW state by other driver.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
LOGIC SYMBOL
GTL2006
GTL VREF 1AO LVTTL OUTPUTS 2AO 3 1 2 27 1BI GTL INPUTS 2BI
26
5A (OPEN DRAIN) LVTTL I/O 6A (OPEN DRAIN)
4
25
7BO1
5
24
7BO2
GTL OUTPUTS
LVTTL INPUT 8AI GTL INPUT 11BI
6 7
23 22 DELAY1 21
8BO 11BO
LVTTL I/O 11A (OPEN DRAIN)
8 9
5BI
GTL INPUT 9BI
DELAY1 20 6BI GTL INPUTS
3AO LVTTL OUTPUTS 4AO
10
19
3BI
11
18
4BI
17 10AI1 LVTTL INPUTS 10AI2 12 16 13
10BO1 GTL OUTPUTS 10BO2
15
9AO LVTTL OUTPUT
SW01092
NOTE: 1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. Figure 2. Logic symbol
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
APPLICATION INFORMATION
VTT 56 VCC 1.5 k to 1.2 k 1.5 k 2R R 56
VTT
PLATFORM HEALTH MANAGEMENT VREF CPU1 IERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L FORCEPR_L NMI_L 1AO 2AO 5A 6A 8AI 11BI 11A 9BI CPU2 IERR_L CPU2 THRMTRIP L CPU1 SMI L CPU2 SMI L SMI_BUFF_L 3AO 4AO 10AI1 10AI2 GND VCC 1BI 2BI 7BO1 7BO2 8BO 11B0 5BI 6BI 3BI 4BI 10BO1 10BO2 9AO
VCC CPU1 IERR_L THRMTRIP L FORCEPR_L PROCHOT L NMI CPU1 SMI L
FORCEPR_L PROCHOT L IERR_L THRMTRIP L NMI CPU2 SMI L CPU2
GTL2006
SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L OPTIONAL SIGNAL LINE
SW01094
Figure 3. Application diagram
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
Frequently Asked Questions
Question 1: On the GTL2006 LVTTL inputs, specifically 10AI1 and 10AI2, when the GTL2006 is unpowered, these inputs may be pulled up to 3.3 V S/B and we want to make sure that there is no leakage path to the power rail under this condition. Are the LVTTL inputs HIGH Impedance when the device is unpowered and will there be any leakage? Answer 1: When the device is unpowered, the LVTTL inputs will be in a high-impedance state and will not leak to VDD if they are pulled high while the device is unpowered. Question 2: Do all the LVTTL inputs have the same unpowered characteristic? Answer 2: Yes. Question 3: What is the condition of the other GTL I/O and LVTTL output pins when the device is unpowered? Answer 3: The open drain outputs, both GTL and LVTTL, will not leak to the power supply if they are pulled high while the device is unpowered. The GTL inputs will also not leak to the power supply under the same conditions. The LVTTL totem pole outputs, however, are not open drain type outputs and there will be current flow on these pins if they are pulled high when VDD is at ground. Question 4: When this sequence occurs: 1) Pin 11BI is driven LOW (at time t0) 2) Pin 11A is driven LOW (at time t1) 3) Pin 11BI stops driving LOW (at time t2) 4)Pin 11A stops driving LOW (at time t3) Are there wired-OR glitches at pin 11BO at time t1 and t2? Answer 4: The output of 11BI is physically wired to the 11A pin. There will be no glitch at t1 when the external driver turns on and drives LOW, unless the external driver is a long distance away and the pull-up is a low value. If the pull-up R = ZO of the line and the current were equally shared, the bounce would be to 1/2 the pull-up voltage, presumably VDD. The input is a 1/2 VDD threshold input, so the glitch may propagate to the 11BO. If the glitch is very short it may not propagate, or if the pull-up were higher the amplitude would be too small to propagate, or if the external driver were sinking more than half of the total current, it would not propagate. If the external driver is weak and a long way away you will most likely see a glitch on 11BO, because there will be a large glitch on 11A. Question 5: Can you give us some guideline on how high the pull-up resistor value at pin 11A needs to be to avoid glitches on 11BO? Answer 5: The 11A pin is a TTL pin, generally the pull-up resistor used on TTL pins are chosen to minimize power rather than to match the line impedance. Most line impedances are in the range of 50 . If the pull-up is 3 x ZO, that is 150 ; even if all the current is being sunk by the GTL2006, the initial bounce on 11A would only be 1/ V , and would only last for the round trip time to the external 3 DD driver, provided that the external driver can sink all of the current, the bounce will return LOW. The 1/3 VDD is not a high level to the GTL2006 11A pin, so no bounce would show up on the 11BO pin. Normal choices for the pull-up on 11A would be in the 1 k to several k range, depending on speed and current considerations. Question 6: Please explain the timing specification of Bn to Bn in the AC Characteristics table. Which specific inputs/outputs does it cover, and why is the H > L transition so slow? Answer 6: The Bn to Bn refers to the 4BI to 7BO1 path and to the 6BI to 7BO2 path. The times are disable and enable times since a LOW on 5BI or 6BI should not be reflected as a LOW on 7BO1 or 7BO2. The tPLH corresponds to the disable time, and the tPHL corresponds to the enable time. The enable time is deliberately slow to prevent glitches/false LOWs on the 7BOn outputs, because a LOW on 5BI drives a LOW on 5A, which is an open-drain I/O and may have a slow rise time. And a LOW on 6BI drives a LOW on 6A that is an open-drain I/O that may also have a slow rise time. Question 6A: Now that I try to examine the circuit from the data sheet, I am just a little bit concerned. Let me try to describe the function first: This circuit is used for monitoring and driving the CPU PROCHOT#. The monitor device is a Heceta7 part and its output is bi-directional, CPU1_PROCHOT# and is connected to 5A. The CPU has an output called PROCHOT#, which goes to 5BI and an input call FRCPROCHOT# that comes from 7BO1. When the CPU is generating PROCHPT# (5BI), we do not want the CPU input FRCPROCHOT# (7BO1) to also see this signal. Scenario 1: CPU driving PROCHOT# - 5BI input is HIGH and goes LOW; output 5A is HIGH and goes LOW following 5BI. The output 7BO should stay HIGH. - 5BI input is LOW and goes HIGH; output 5A is LOW and goes HIGH following 5BI. The output 7BO1 should stay HIGH. Scenario 2: Heceta7 driving CPU1_PROCHOT# - 5A input is HIGH and goes LOW; output 7BO1 is HIGH and goes LOW following 5A. The input 5BI should stay HIGH. - 5A input is LOW and goes HIGH; output 7BO1 is LOW and goes HIGH following 5A. The output 5BI should stay HIGH. Now I can see the reason for the delay in the enable path so that we keep the output disabled to account for the potentially slow riser time on 5A. In my mind, there should also be a delay block shown in the path 5BI to 5A so that the 5BI H-to-L can disable the driver for 7BO1 before the signal appears on the 5A input/output, thus appearing as an input to the driver for 7BO1. Have you characterized what sort of glitch you get on the 7BO1 output on an H-to-L transition on 5BI? Answer 6A: The disable for 7BO1 comes directly from the internal 5BI signal, and by design it always disables the LOW on 7BO1 before the LOW on the 5BI can propagate to the 5AI/O and back to the 7BO1. Question 7: Can I operate the GTL2006 at VTT of 1.2 V and VREF of 0.6 V? Answer 7: Yes; you can operate VTT up to 3.6 V and VREF between 0.5 V to 1.8 V at any VTT to adjust the high and low noise margins to your application. You don't have to follow the GTL-/GTL/GTL+ specifications. The GTL VIL and VIH will be 50 mV around VREF within the range of 0.5 V to 1.8 V.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO OL IOH Tstg TJ(MAX) PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 Current into any output in the LOW state Current into any output in the HIGH state Storage temperature range Maximum junction temperature VI < 0 V A port (LVTTL) B port(GTL) VO < 0 V Output in Off or HIGH state; A port Output in Off or HIGH state; B port A port B port A port CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to +4.6 32 30 -32 -60 to +150 +125 UNIT V mA V V mA V V mA mA mA C C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VTT PARAMETER Supply voltage GTL- Termination voltage GTL GTL+ Overall VREF Supply voltage GTL- GTL GTL+ VI VIH VIL IOH IO OL Tamb Input voltage HIGH-level HIGH level input voltage LOW-level LOW level input voltage HIGH-level output current LOW-level LOW level output current Operating free-air temperature range A port B port A port B port A port B port A port A port B port CONDITIONS MIN 3.0 0.85 1.14 1.35 0.5 0.5 0.76 0.87 0 0 2 VREF + 50 mV -- -- -- -- -- -40 TYP 3.3 0.9 1.2 1.5
2/ V 3 TT
MAX 3.6 0.95 1.26 1.65 1.8 0.63 0.84 1.10 3.6 3.6 -- -- 0.8 VREF - 50 mV -16 16 15 85
UNIT V V
0.6 0.8 1.0 3.3 VTT -- -- -- -- -- -- -- --
V
V V V mA mA mA C
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VO OH VO OL A port A port B port A port B port ICC ICC CIO O
3
-40 C to +85 C TYP1 -- -- -- -- -- -- -- -- -- 7.8 4.5 MAX -- -- 0.8 0.4 1 1 1 12 500 -- -- VCC-0.2 2.1 -- -- -- -- -- -- -- -- --
UNIT
VCC = 3.0 V to 3.6 V; IOH = -100 A VCC = 3.0 V; IOH = -16 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 15 mA VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V VCC = 3.6 V; VI = VTT or GND VCC = 3.6 V;VI = VCC or GND; IO = 0 mA VCC = 3.6 V; VI = VCC - 0.6 V VO = 3.0 V or 0 V VO = VTT or 0 V
V V
II
A mA A pF
A or B port A port or control inputs A port B port
NOTES: 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
AC CHARACTERISTICS (3.3 V 0.3 V RANGE)
LIMITS (GTL-) SYMBOL PARAMETER WAVEFORM VCC = 3.3 V 0.3 V VREF = 0.6 V MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL2 tPLZ tPZH An to Bn Bn to An 9BI to 10BOn 11BI to 11BO Bn to An (I/O) 3 1 2 2 2 2 2 2 2 2 2 2 2 TYP1 4 5.5 5.5 5.5 6 6 8 14 5 5 MAX 8 10 10 10 11 11 13 21 10 10 LIMITS (GTL) VCC = 3.3 V 0.3 V VREF = 0.8 V MIN 2 2 2 2 2 2 2 2 2 2 TYP1 4 5.5 5.5 5.5 6 6 8 14 5 5 MAX 8 10 10 10 11 11 13 21 10 10 LIMITS (GTL+) VCC = 3.3 V 0.3 V VREF = 1.0 V MIN 2 2 2 2 2 2 2 2 2 2 TYP1 4 5.5 5.5 5.5 6 6 8 14 5 5 MAX 8 10 10 10 11 11 13 21 10 10 ns ns ns ns ns ns UNIT
tPLH 4 7 11 4 7 11 4 7 11 Bn to Bn 3 tPHL 120 205 350 120 205 350 120 205 350 NOTES: 1. All typical values are at VCC = 3.3 V and Tamb = 25 C. 2. Includes 7.6 ns RC rise time of test load pull-up on 11A, 1.5 k pull-up and 21 pF load on 11A has about 23 ns RC rise time.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
AC WAVEFORMS
VM = 1.5 V at VCC 3.0 V for A ports; VM = VREF for B ports
tpulse VH VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VM = 1.5 V for A port and VREF for B port VH = 3 V for A port and VTT for B port Output 3.0 V Input VOL 1.5 V 1.5 V 0V tPLH tPHL VOH Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES A port to B port INPUT 1.5 V 1.5 V 0V 3.5 V 1.5 V 3V PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. 1.5 V 1.5 V tPLH tPHL VOH Input VREF VREF 0V VTT
SW00469
Waveform 2.
SW01093
Waveform 1.
OUTPUT
tPZL
tPLZ
VOL + 0.3 V
SW02235
Waveform 3.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
PERFORMANCE CURVES
1100 VCC = 3.0 V Tamb = -40 C 1000 Vref (mV) VTH+ VTH- 1000 1100 VCC = 3.3 V Tamb = +25 C Vref (mV) VTH+ VTH-
900
900
VTH+ and VTH- (mV)
800
VTH+ and VTH- (mV) 0.6 0.7 Vref (V) 0.8 0.9 1.0
800
700
700
600
600
500
500
400 0.5
400 0.5
0.6
0.7 Vref (V)
0.8
0.9
1.0
1100 VCC = 3.6 V Tamb = +85 C 1000 Vref (mV) VTH+ VTH-
900
VTH+ and VTH- (mV)
800
700
600
500
400 0.5
0.6
0.7 Vref (V)
0.8
0.9
1.0
SW02255
Figure 4. GTL VTH+ and VTH- versus VREF
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
TEST CIRCUIT
VCC VCC VO D.U.T. VI RT 50 pF CL RL = 500 PULSE GENERATOR RT D.U.T. CL 30 pF VO VTT
VI PULSE GENERATOR
50
Test circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SW02066
Figure 7. Load circuit for B outputs
SW00471
Figure 5. Load circuitry for A outputs
VCC
2 x VCC
VI PULSE GENERATOR RT D.U.T.
VO 50 pF CL
RL = 500
RL = 500
Test Circuit for open drain LVTTL I/O DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SW02067
Figure 6. Load circuitry for open drain LVTTL I/O
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
2004 Jun 21
12
Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
REVISION HISTORY
Rev _2 Date 20040621 Description Product data (9397 750 13063). Supersedes data of 2003 Dec 18. Modifications:
* All figures numbered. * Figure 2, "Logic symbol" modified. * Page 6, Frequently asked Questions: add questions/answers 4, 5, 6, 6A, and 7. * Page 8, AC Characteristics (3.3 V 0.3 Range); tPHL An to Bn, GTL+ maximum: change from `1. ns' to `10 ns'. * Add "Performance curves" section on page 10.
_1 20031218 Product data (9397 750 12562); ECN 853-2440 01-A14985 dated 15 December 2003.
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Philips Semiconductors
Product data
13-bit GTL-/GTL/GTL+ to LVTTL translator
GTL2006
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 06-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 13063
Philips Semiconductors
2004 Jun 21 14

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